this datasheet contains new product informa tion. anachip corp. reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/9 features peel? 18cv8 -7/-10/-15/-25 cmos programmable electrically erasable logic device multiple speed power, temperature options - v cc = 5 volts 10% - speeds ranging from 7ns to 25 ns - power as low as 37ma at 25mhz - commercial and industrial versions available cmos electrically erasable te c hn ol o gy - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs development / programmer support - third party software and programmers - winplace development software - pld-to-peel? jedec file translator architectural flexibility - enhanced architecture fits in more logic - 74 product terms x 36 input and array - 10 inputs and 8 i/o pins - 12 possible macrocell configurations - asynchronous clear - independent output enables - 20 pin dip/soic/tssop and plcc application versatility - replaces random logic - super sets plds (pal, gal, epld) - enhanced architecture fits more logic than ordinary plds general description the peel?18cv8 is a programmable electrically erasable logic (peel?) device providing an attractive alternative to ordinary plds. the peel?18cv8 offers the performance, flex- ibility, ease of design and production practicality needed by logic designers today. the peel?18cv8 is available in 20-pin dip, plcc, soic and tssop packages with speeds ranging from 7ns to 25ns with power consumption as low as 37ma. ee-reprogrammability provides the convenience of instant reprogramming for develop- ment and reusable production inventory minimizing the impact of programming changes or errors. ee-reprogrammability also improves factory testability, thus assuring the highest quality pos- sible. figure 2 pin configuration the peel?18cv8 architecture allows it to replace over 20 stan- dard 20-pin plds (pal, gal, epld etc.). it also provides addi- tional architecture features so more logic can be put into every design. anachip?s jedec file translator instantly converts to the peel?18cv8 existing 20-pin plds without the need to rework the existing design. development and programming support for the peel?18cv8 is provided by popular third-party program- mers and development software. figure 3 block diagram i/clk 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 gnd 10 20 vcc 19 i/o ? 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i dip tssop plcc soic
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/9 figure 4 peel?18cv8 logic array diagram
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/9 function description the peel?18cv8 implements logic functions as sum-of- prod- ucts expressions in a programmable-and/fixed-or logic array. user-defined functions are created by programming the connec- tions of input signals into the array. user-configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the peel?18cv8 architecture is illustrated in the block dia- gram of figure 3. ten dedicated inputs and 8 i/os provide up to 18 inputs and 8 outputs for creation of logic functions. at the core of the device is a programmable electrically-erasable and array which drives a fixed or array. with this structure, the peel?18cv8 can implement up to 8 sum-of-products logic expressions. associated with each of the 8 or functions is an i/o macrocell which can be independently programmed to one of 12 different configurations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the and array. and/or logic array the programmable and array of the peel?18cv8 (shown in figure 4) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 36 input lines: - 20 input lines carry the true and complement of the signals applied to the 10 input pins - 16 additional lines carry the true and complement values of feedback or input signals from the 8 i/os 74 product terms: - 64 product terms (arranged in groups of 8) are used to form sum of product functions - 8 output enable terms (one for each i/o) - 1 global synchronous preset term - 1 global asynchronous clear term at each input-line/product-term intersection, there is an eeprom memory cell that determines whether or not there is a logical connection at that intersection. each product term is essentially a 36-input and gate. a product term that is con- nected to both the true and complement of an input signal will always be false and thus will not affect the or function that it drives. when all the connections on a product term are opened, a ?don?t care? state exists and that term will always be true. when programming the peel?18cv8, the device programmer first performs a bulk erase to remove the previous pattern. the erase cycle opens every logical connection in the array. the device is configured to perform the user-defined function by pro- gramming selected connections in the and array. (note that peel? device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). programmable i/o macrocell the unique twelve-configuration output macrocell provides com- plete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the peel?18cv8 to the precise requirements of their designs. macrocell architecture each i/o macrocell, as shown in figure 4, consists of a d-type flip-flop and two signal-select multiplexers. the configuration of each macrocell is determined by the four eeprom bits control- ling these multiplexers. these bits determine output polarity, out- put type (registered or non-registered) and input-feedback path (bidirectional i/o, combinatorial feedback). refer to table 1 for details. equivalent circuits for the twelve macrocell configurations are illustrated in figure 4. in addition to emulating the four pal-type output structures (configurations 3,4,9, and 10), the macrocell provides eight additional configurations. when creating a peel? device design, the desired macrocell configuration gen- erally is specified explicitly in the design file. when the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the jedec programming file. output type the signal from the or array can be fed directly to the output pin (combinatorial function) or latched in the d-type flip-flop (regis- tered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. when the synchronous preset term is satisfied, the q out- put of the register will be set high at the next rising edge of the clock input. satisfying the asynchronous clear will set q low, regardless of the clock state. if both terms are satisfied simulta- neously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control of its associated programmable output enable product term. when the logical conditions progra mmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is switched into the high-impedance state. under the control of the output enable term, the i/o pin can func- tion as a dedicated input, a dedicated output, or a bi-directional i/ o. opening every connection on the output enable term will per- manently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/9 always be logically false and the i/o will function as a dedicated input. input/feedback select the peel?18cv8 macrocell also provides control over the feedback path. the input/feedback signal associated with each i/ o macrocell may be obtained from three different locations; from the i/o input pin, from the q output of the flip-flop (registered feedback), or directly from the or gate (combinatorial feed- back). bi-directional i/o the input/feedback signal is taken from the i/o pin when using the pin as a dedicated input or as a bi-directional i/o. (note that it is possible to create a registered output function with a bi-direc- tional i/o.) combinatorial feedback the signal-select multiplexer gives the macrocell the ability to feedback the output of the or gate, bypassing the output buffer, regardless of whether the output function is registered or combi- natorial. this feature allows the creation of asynchronous latches, even when the output must be disabled. (refer to configurations 5,6,7 and 8 in figure 4.) registered feedback feedback also can be taken from the register, regardless of whether the output function is to be combinatorial or registered. when implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output. design security the peel?18cv8 provides a special eeprom security bit that prevents unauthorized reading or copying of designs pro- grammed into the device. the security bit is set by the pld pro- grammer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit is set it is impossible to verify (read) or program the peel? until the entire device has first been erased with the bulk-erase function. programming support anachip?s jedec file translator allows easy conversion of exist- ing 20 pin pld designs to the peel?18cv8, without the need for redesign. anachip also offers (for free) its proprietary win- place software, an easy-to-use entry level pc-based software development system. programming support includes all the popular third party pro- grammers: bp microsystems, system general, logical devices, and numerous others. figure 4 block diagram of the peel?18cv8 i/o macrocell
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/9 figure 4 equivalent circuits for the twelve configurations of the peel?18cv8 i/o macrocell
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/9 absolute maximum ratings this device has been designed and tested for the specified operat- ing ranges. improper operation outside of these levels is not guaran- teed. exposure to absolute maximum ratings may cause permanent damage. operating range d.c. electrical characteristics over the operating range (unless otherwise specified)
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/9 a.c. electrical characteristics over the operating range 8 switching waveforms inputs, i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs notes: 1. minimum dc input is -0.5v, however, inputs may undershoot to -2.0v for peri- ods less than 20 ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and vcc in t r and t f are referenced at the 10% and 90% levels. 4. i/o pins are 0v and v cc . 5. ?input? refers to an input pin signal. 6. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l. 7. capacitances are tested on a sample basis. 8. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. test one output at a time for a duration of less than 1 second. 10. i cc for a typical application: this parameter is tested with the device pro- grammed as an 8-bit counter. 11. parameters are not 100% tested. specifications are based on initial character- ization and are tested after any design process modification that might affect oper- ational frequency. 12. available only for 18cv8 -15/i-15/-25/i-25 grades 13. 24ma available for 18cv8-5/-7. all other speeds are 16ma.
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/9 peel? device and array test loads ordering information part number speed temperature package peel18cv8p-7 (l) 7.5 ns commercial 20-pin plastic 300 mil dip PEEL18CV8J-7 (l) 7.5 ns commercial 20-pin plastic (j) leaded chip carrier (plcc) peel18cv8s-7 (l) 7.5 ns commercial 20-pin soic peel18cv8p-10 (l) commercial peel18cv8pi-10 (l) 10 ns industrial 20-pin plastic 300 mil dip peel18cv8j-10 (l) commercial peel18cv8ji-10 (l) 10 ns industrial 20-pin plastic (j) leaded chip carrier (plcc) peel18cv8s-10 (l) commercial peel18cv8si-10 (l) 10 ns industrial 20-pin soic peel18cv8t-10 (l) commercial peel18cv8ti-10 (l) 10 ns industrial 20-pin tssop 170 mil peel18cv8p-15 (l) commercial peel18cv8pi-15 (l) 15 ns industrial 20-pin plastic 300 mil dip peel18cv8j-15 (l) commercial peel18cv8ji-15 (l) 15 ns industrial 20-pin plastic (j) leaded chip carrier (plcc) peel18cv8s-15 (l) commercial peel18cv8si-15 (l) 15 ns industrial 20-pin soic peel18cv8t-15 (l) commercial peel18cv8ti-15 (l) 15ns industrial 20-tssop 170 mil peel18cv8p-25 (l) commercial peel18cv8pi-25 (l) 25 ns industrial 20-pin plastic 300 mil dip peel18cv8j-25 (l) commercial peel18cv8ji-25 (l) 25 ns industrial 20-pin plastic (j) leaded chip carrier (plcc) peel18cv8s-25 (l) commercial peel18cv8si-25 (l) 25 ns industrial 20-pin soic peel18cv8t-25 (l) commercial peel18cv8ti-25 (l) 25 ns industrial 20-pin tssop 170 mil
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/9 part number peel tm 18cv8 pi-25x package p = 20-pin plastic 300mil dip s = 20-pin soic 300 mil gullwing temperature range (blank) = commercial 0 to +70 o c speed -7 = 7.5ns t pd lead free blank : normal l : lead free package j = 20-pin plastic (j) leaded chip carrier (plcc) suffix device t = 20-pin tssop 170mil i = industrial -40 to +85 o c -10 = 10ns t pd -15 = 15ns t pd -25 = 25ns t pd anachip corp. head office, 2f, no. 24-2, industry e. rd. iv, science-based industrial park, hsinchu, 300, taiwan tel: +886-3-5678234 fax: +886-3-5678368 anachip usa 780 montague expressway, #201 san jose, ca 95131 tel: (408) 321-9600 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and without notice. the information furnished by anachip in this publi cation is believed to be accurate and reliable. however, there is no responsibility assumed by an achip for its use nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of anachip. anachip?s products are not authorized for use as critical components in life support devices or systems. marks bearing ? or ? are registered trademarks and trademarks of anachip corp.
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